1. Field of the Invention
The present invention relates to a semiconductor memory such as an SRAM (static random access memory) having flip-flop memory cells.
2. Description of the Related Art
FIG. 1 is a plan view schematically showing a conventional SRAM. Numeral 1 denotes a chip proper, 2 an array of memory cells, 3 a bit line pair, 4 a data fetching gate, 5 a data bus, and 60 to 63 output ports (pads). The data bus 5 for bit pairs is connected to output circuits (not shown) corresponding to the output ports 60 to 63. Other pads such as power source pads, are omitted in the figure.
This conventional SRAM is based on DIP (dual in-line package) pin arrangement standards of JEDEC (Joint Electronic Device Engineering Council). The bit line pairs 3 extend in parallel with short sides 7 and 8 of an element forming a plane of the chip 1. The output ports 60 and 61 are disposed along the short side 7 in the vicinity of a long side 9, while the output ports 62 and 63 are disposed along the short side 7 in the vicinity of another long side 10.
Since the storage capacity of this conventional SRAM is not so large, the chip area thereof is not so wide and the output ports 60 and 61 are not so distanced away from the output ports 62 and 63.
In recent years, however, storage capacities of SRAMs are increasing, thereby increasing chip areas and widening distances between output ports. These factors result in elongating data buses, which hinder high-speed operation of the SRAMs.